System, USB Type-C connector and method to transmit encoded data

ABSTRACT

A system, USB Type-C connector and method are provided herein to transmit encoded data across a USB cable from a transmitter circuit included within a transmitting port of a USB Type-C connector. The method described herein may generally include detecting a voltage generated at a configuration channel (CC) pin of a transmitting port of a USB Type-C connector, setting a voltage at an output node of the transmitter circuit equal to the voltage detected at the CC pin before the output node of the transmitter circuit is connected to the CC pin, subsequently connecting the output node of the transmitter circuit to the CC pin, and transmitting the encoded data from the transmitter circuit through the CC pin to the USB cable.

BACKGROUND 1. Field of the Disclosure

This disclosure relates to USB Type-C connectors and, more particularly,to a USB Type-C connector and method to transmit Bi-phase Mark Coding(BMC) encoded data signals across a configuration channel (CC) line of aUSB cable.

2. Description of the Relevant Art

The following descriptions and examples are provided as background onlyand are intended to reveal information that is believed to be ofpossible relevance to the present disclosure. No admission isnecessarily intended, or should be construed, that any of the followinginformation constitutes prior art impacting the patentable character ofthe subject matter claimed herein.

Electronic devices are often equipped with various types of interfaces,which enable power and/or data delivery to and from the device. Oneexample of such an interface is the Universal Serial Bus (USB)interface. USB is an industry standard developed by the USB ImplementersForum (USB IF), which defines characteristics of the cables, connectorsand communications protocols used in a bus for connection,communication, and power delivery between computers and electronicdevices. USB is currently used in many different types of devices (suchas desktops, laptops, tablets, mobile phones, PDAs, etc.) andaccessories (such as keyboards, mice, power supplies and chargers, sparebattery packs, docking stations, external hard drives, audio headsets,speakers, cameras, etc.). USB interfaces may take various forms,including both wired and wireless interfaces, and enable devices andaccessories to communicate according to a variety of data communicationstandards, such as USB 1.0, USB 2.0, USB 3.0, and USB 3.1, as well asany future revisions thereof.

In 2015, the USB IF released the USB Type-C Cable and ConnectorSpecification (v1.1) and USB Power Delivery Revision 2.0 Specification(v1.1). The USB Type-C Cable and Connector Specification describesreceptacle and plug (collectively referred to herein as “connectors”)and cable configurations that provide a smaller, thinner and more robustalternative to the USB 3.1 interface (i.e., Standard and Micro USBcables and connectors). USB Type-C receptacles are intended for usewithin very thin platforms, such as ultra-thin laptops, tablets andsmartphones, where existing Standard and Micro USB receptacles aredeemed too large. The USB Type-C plug provides greater ease of use byenabling the plug to be inserted into the receptacle right side-up orupside-down, while the USB Type-C cable enhances ease of use by beingplug-able in either direction between host and device. Functional signalplans for a USB Type-C receptacle interface 10 and a USB Type-C pluginterface 26 are illustrated in FIGS. 1 and 2.

As shown in FIG. 1, USB Type-C receptacle interface 10 provides twopairs of power pins (Vbus) 12, two pairs of ground pins (GND) 14, twodifferential pairs of USB 2.0 data bus pins (D+/−) 16, four pairs of USB3.1 high speed data bus pins (TX and RX) 18, two sideband use pins(SBU1, SBU2) 20 and two configuration channel pins (CC1, CC2) 22.Similar to receptacle interface 10, USB Type-C plug interface 26provides two pairs of power pins (Vbus) 12, two pairs of ground pins(GND) 14, four pairs of USB 3.1 high speed data bus pins (TX and RX) 18,and two sideband use pins (SBU1, SBU2) 20. Unlike receptacle interface10, however, plug interface 26 comprises only one differential pair ofUSB 2.0 data bus pins (D+/−) 16 and only one configuration channel pin(CC) 22. In addition, plug interface 26 includes a voltage connect pin(V_(CONN)) 24 to provide power to circuits within the plug. When pluginterface 26 is inserted into receptacle interface 10, one of the CCpins (CC1 or CC2) in the receptacle interface 10 is connected to the CCpin in the plug interface 26 through the cable to establish signalorientation. The other CC pin (CC1 or CC2) in receptacle interface 10 isrepurposed as V_(CONN) for powering circuits within the plug.

The configuration channel pins are generally used for detecting cableattach and detach, detecting plug orientation (i.e., right side-up orupside-down), and establishing Vbus current. In USB Type-C connectors,the CC pins are also used for transmitting and receiving USB PowerDelivery (PD) communication messages for establishing power contractsthat allow voltage and current levels, which are outside those definedby the USB 2.0 and USB 3.1 Specifications, changing the port sourcingVbus or V_(CONN), swapping port roles (e.g., between source and sink, ordownstream facing port, DFP, and upstream facing port, UFP) andcommunicating with cables. The USB Power Delivery Specification Revision2.0 provides methods and specifications for communicating USB PDcommunication messages between different types of USB connectors (e.g.,USB Type-A, -B and -C) and legacy applications. Failure to meet thesespecifications may cause several undesirable problems, such as creatinga source of electromagnetic interference (EMI) and power loss, andfalsely triggering a USB Type-C receiver to turn on.

SUMMARY

The following description of various embodiments of systems, USB Type-Cconnectors and methods is not to be construed in any way as limiting thesubject matter of the appended claims.

Generally speaking, the present disclosure provides a USB system, USBType-C connector and method to transmit Bi-phase Mark Coding (BMC)encoded data signals across a configuration channel (CC) line of a USBcable connecting a transceiver within a transmitting port to atransceiver within a receiving port of the USB system. In the presentdisclosure, additional circuitry is provided within the USB Type-Cconnector to control the slew rate of each transition, or edge, of a BMCencoded data signal transmitted from the transceiver circuit, whilemeeting the rise and fall times set forth in the PD specification. Theadditional circuitry and methods described herein enable the transceivercircuit to control the slew rate and meet the specified rise and falltimes during all transitions of the BMC encoded data signal, includingthe initial transition from the high impedance state to the logic ‘0’state and each subsequent rising and falling edge transition. In doingso, the additional circuitry and methods described herein avoid manyundesirable problems, such as voltage ringing on the CC line, reducedpower efficiency during start transmission, and false triggering of areceiver within an upstream USB Type-C connector.

According to one embodiment, a system is provided herein comprising afirst USB Type-C connector coupled to a second USB Type-C connector viaa USB cable. According to another embodiment, a method is providedherein to transmit encoded data across a USB cable from a transceivercircuit included within a transmitting port of a first USB Type-Cconnector to a transceiver circuit included within a receiving port of asecond USB Type-C connector. Since the encoded data may be transmittedacross the USB cable in either direction (i.e., from the first USBType-C connector to the second USB Type-C connector, and vice versa),the first and second USB Type-C connectors may each include transceivershaving transmitter circuitry and receiver circuitry. At least some ofthe additional circuitry described herein may be provided within thetransmitter circuits included within the transceivers of the first andsecond USB Type-C connectors for controlling the slew rate of the BMCencoded data signals transmitted from either connector.

In accordance with the present disclosure, a USB Type-C connector (e.g.,the first USB Type-C connector) may include at least one configurationchannel (CC) pin, a plurality of switches coupled to the at least one CCpin, a transmitter circuit and a controller. The transmitter circuit mayhave an output node, which may be switchably coupled to the at least oneCC pin to transmit encoded data across the USB cable to a CC pin ofanother USB Type-C connector (e.g., the second USB Type-C connector).The controller may be coupled and configured to supply a sequence ofcontrol signals to the transmitter circuit and to the plurality ofswitches to set a voltage at the output node of the transmitter circuitequal to a voltage generated at the at least one CC pin before theoutput node of the transmitter circuit is connected to the at least oneCC pin to transmit the encoded data across the USB cable.

According to one embodiment, the transmitter circuit may include amultiplexer and an amplifier in addition to other circuitry, which maytypically be used to encode and drive the BMC encoded data signals. Themultiplexer may include a first input coupled to receive encoded data, asecond input coupled via a first one of the switches (i.e., a firstswitch) to the CC pin, a select input, and an output. The amplifier mayinclude a first input coupled to receive the output from themultiplexer, a second input coupled via a second one of the switches(i.e., a second switch) to the at least one CC pin, and an output, whichmay also be the output node of the transmitter circuit. The output ofthe amplifier may be coupled via a fourth one of the switches (i.e., afourth switch) to the second input of the amplifier, and may be furthercoupled via a fifth one of the switches (i.e., a fifth switch) to the atleast one CC pin. In some embodiments, a pull-down resistor may becoupled between the at least one CC pin and a third one of the switches(i.e., a third switch), which is coupled to ground. In otherembodiments, a third one of the switches may be coupled between acurrent source (or voltage source and pull-up resistor) and the at leastone CC pin.

According to one embodiment, a method is provided herein fortransmitting encoded data across a USB cable from a transmitter circuitincluded within a transmitting port of a first USB Type-C connector to areceiver circuit included within a receiving port of a second USB Type-Cconnector. In general, the method may include detecting a voltagegenerated at the CC pin of the transmitting port, setting a voltage atan output node of the transmitter circuit equal to the voltage generatedat the CC pin before the output node of the transmitter circuit isconnected to the CC pin, subsequently connecting the output of thetransmitter circuit to the CC pin, and transmitting the encoded datafrom the transmitter circuit through the CC pin to the USB cable.

According to one embodiment, the controller described herein may beconfigured to supply a sequence of control signals to the select inputof the multiplexer and to the first, second, third, fourth and fifthswitches to implement the method described herein. For example, thecontroller may supply open signals to the first, second and fifthswitches to disconnect the output of the amplifier from the CC pin, andmay supply close signals to the third and fourth switches. In somecases, the third and fourth switches may be closed prior to opening thefirst, second and fifth switches. For example, the third switch may beclosed upon designating the transmitting port of the first USB Type-Cconnector as either an upstream facing port (UFP) or a downstream facingport (DFP). By closing the third switch, current flow may be establishedfrom the current source (or voltage source and pull-up resistor) in oneport through the pull-down resistor and ground connection in anotherport, and a voltage may be generated at the CC pin. By closing thefourth switch, the output of the amplifier is tied to the second inputof the amplifier.

To detect the voltage generated at the CC pin of the transmitting portand set the voltage at the output node of the transmitter circuit equalto the voltage generated at the CC pin, the controller may supply aselect signal to the multiplexer for selecting the second input of themultiplexer, and a close signal to the first switch to set the voltageat the amplifier output equal to the voltage at the CC pin. After thevoltage at the amplifier output is equalized to the voltage at the CCpin, the controller may supply a select signal to the multiplexer forselecting the first input of the multiplexer, an open signal to thefirst switch, and close signals to the second and fifth switches toconnect the amplifier output to the CC pin and transmit the encoded datafrom the transmitter circuit through the CC pin to the USB cable. Soonafter the fifth switch is closed, the controller may supply an opensignal to the fourth switch.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the disclosure will become apparent uponreading the following detailed description and upon reference to theaccompanying drawings.

FIG. 1 illustrates a functional signal plan for a USB Type-C receptacleinterface;

FIG. 2 illustrates a functional signal plan for a USB Type-C pluginterface;

FIG. 3 illustrates a functional diagram of a USB system comprising afirst dual role port (DRP) connected to a second dual role port (DRP)via a USB cable having a configuration channel (CC) line;

FIG. 4A illustrates a simplified circuit diagram of circuitry added to aDRP (configured as an upstream facing port, UFP) for transmittingencoded data across the CC line of a USB cable;

FIG. 4B illustrates a simplified circuit diagram of circuitry added to aDRP (configured as a downstream facing port, DFP) for transmittingencoded data across the CC line of a USB cable;

FIG. 5A illustrates a more detailed circuit diagram of the additionalcircuitry shown in FIG. 4A, according to one embodiment;

FIG. 5B illustrates a more detailed circuit diagram of the additionalcircuitry shown in FIG. 4B, according to one embodiment;

FIG. 6 is a flowchart diagram illustrating one embodiment of a method totransmit encoded data across the CC line of a USB cable;

FIG. 7 is a circuit diagram illustrating additional circuit elementsthat may be included within the additional circuitry shown in FIGS. 4-5to ensure that the CC pin voltage is accurately sensed;

FIG. 8 is an exemplary state diagram for a controller; and

FIG. 9 is a graph illustrating the slew rate control provided by theadditional circuitry and method disclosed herein.

While the system, USB Type-C connectors and methods disclosed herein aresusceptible to various modifications and alternative forms, specificembodiments thereof are shown by way of example in the drawings and willherein be described in detail. It should be understood, however, thatthe drawings and detailed description thereto are not intended to limitthe disclosure to the particular form disclosed, but on the contrary,the intention is to cover all modifications, equivalents andalternatives falling within the spirit and scope of the presentdisclosure as defined by the appended claims.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present disclosure is directed to systems, electronic devices andaccessories including USB Type-C connectors, which may be a USB Type-Creceptacle and/or plug, as described in the USB Type-C Cable andConnector Specification (v1.x). In particular, the present disclosureprovides a system, USB Type-C connector and method to transmit Bi-phaseMark Coding (BMC) encoded data signals across a configuration channel(CC) line of a USB cable connecting a transceiver within a transmittingport to a transceiver within a receiving port of the USB system. In thepresent disclosure, additional circuitry provided within the USB Type-Cconnector enables the transceiver circuit to control the slew rate andmeet the rise and fall times specified in the USB Power DeliveryRevision 2.0 Specification (v1.1) during all transitions of the BMCencoded data signal, including the initial transition from the highimpedance state to the logic ‘0’ state and each subsequent rising andfalling edge transition. In doing so, the additional circuitry andmethods described herein avoid many undesirable problems, such asvoltage ringing on the CC line, reduced power efficiency during starttransmission, and false triggering of a receiver within an upstream USBType-C connector.

USB Type-C connectors may be configured to operate as a downstreamfacing port (DFP), an upstream facing port (UFP) or a dual role port(DRP). The port designation or role is generally associated with theflow of data in a USB connection. For example, a port on a host may bedesignated as a DFP for “sourcing” or providing power to a connecteddevice. On the other hand, a port on a connected device may bedesignated as a UFP for “sinking” or consuming the power provided by thehost. In some cases, a host or a device may comprise a DRP, which canoperate as a source, operate as a sink, or alternate between the twoport states. In addition to the physical pins/receptacles needed toestablish electrical contact, a “connector” as described herein alsoincludes the circuitry used to configure and manage power and data flowacross a USB cable.

FIG. 3 illustrates a functional diagram of a system 30 including a firstDRP 32 connected to a second DRP 40 via a USB cable 36 and pads 34/38.As noted above, a DRP may operate as a source when configured as a DFP,a sink when configured as a UFP, or may alternate between the two portstates. In the particular embodiment illustrated in FIG. 3, DRP 32 isconfigured to operate as a DFP and DRP 40 is configured to operate as aUFP. When configured to operate as a DFP, DRP 32 may be a port on a hostor a hub to which one or more devices/accessories are connected. Whenconfigured to operate as a UFP, DRP 40 may be a port on adevice/accessory or hub that connects to a host. As described in moredetail below, the role designation of the first DRP 32 and the secondDRP 40 may be swapped by supplying the appropriate control signals toswitches 42 and 46.

Pads 34 and 38 are illustrated in FIG. 3 as comprising power (Vbus),ground (GND) and configuration channel (CC1 and CC2) pins for thepurpose of explaining port roles (e.g., as a source or sink for Vbus),and the use of the CC pins for detecting cable connection, detectingsignal orientation, and communicating USB PD communication messages. Itwill be understood, however, that pads 34 and 38 may include additionalpins or contacts, as shown in receptacle interface 10 of FIG. 1 anddescribed in the USB Type-C Cable and Connector Specification.

As shown in FIG. 3, each configuration channel pin (CC1 and CC2) in DRP32 and DRP 40 may be connected to a power source (e.g., a supply voltagewithin a range of about 1.7V to 3.6V or about 4.7V to 5.5V) by a pull-upresistor (Rp), and may be further connected to a ground source (GND) bya pull-down resistor (Rd). In some cases, the power source and pull-upresistor (Rp) may be replaced by a current source (Ip), as shown forexample, in FIGS. 4-5. When a port is configured for sourcing power, theCC pins of that port may be connected to the power source via thepull-up resistor (Rp) (or current source, Ip), as shown in DRP 32. Whena port is configured for sinking power, the CC pins of that port may beconnected to ground via the pull-down resistor (Rd), as shown in DRP 40.The CC pins of each port may be connected to the pull-up and pull-downresistors by switches 42 and 46, which are controlled by a configurationchannel (CC) control circuit 44.

As shown in FIG. 3, there are eight possible connections (denoted withdashed and solid lines) between the CC pins of DRP 32 and the CC pins ofDRP 40. When DRP 32 is connected to DRP 40 via cable 36, a connection isestablished through one CC pin (e.g., CC2) on the DFP side and one CCpin (e.g., CC2) on the UFP side, and a current starts to flow throughthe connected CC pins. The CC control circuit 44 of both ports iscoupled through switches 46 for detecting a voltage generated at theconnected CC pin and determining that a connection to a compatibledevice has been established. CC control circuit 44 can also determinethe orientation of the cable plug, depending on whether current flow wasdetected through CC1 or CC2.

Upon determining that a connection has been established, the CC controlcircuit 44 within each port may supply appropriate enable/disablesignals to switches 48 and 50 (depending on the direction of currentflow detected through the CC pins) to establish the direction of currentflow on the Vbus line (i.e., to establish each port 32 and 40 as asource or a sink). For example, if DRP 32 is configured to operate as adownstream facing port (DFP) for providing power to DRP 40, the CCcontrol circuits 44 may supply enable signals to switch 48 of DRP 32 andswitch 50 of DRP 40 and disable signals to switch 50 of DRP 32 andswitch 48 of DRP 40. Doing so would cause current to flow on the Vbusline from a Vbus source coupled to DRP 32 to a Vbus sink coupled to DRP40.

If, on the other hand, DRP 40 is configured to provide power to DRP 32,the CC control circuits 44 may supply the appropriate control signals toswitches 42 and 46 to change the port roles. In FIG. 3, for example, DRP32 may be configured to operate as a UFP by connecting the CC pins ofDRP 32 to pull-down resistors (Rd), and DRP 40 may be configured tooperate as a DFP by connecting the CC pins of DRP 40 to pull-upresistors (Rp). After the port roles are swapped, the CC controlcircuits 44 may supply enable signals to switch 48 of DRP 40 and switch50 of DRP 32 and disable signals to switch 50 of DRP 40 and switch 48 ofDRP 32. This would cause current to flow on the Vbus line from a Vbussource coupled to DRP 40 to a Vbus sink coupled to DRP 32.

In addition to detecting cable attach and detach, detecting plugorientation, and establishing Vbus current, the CC pins of a USB Type-Cconnector may also be used to transmit and receive USB Power Delivery(PD) communication messages. These messages may be communicated for thepurpose of establishing power contracts that allow voltage and currentlevels, which are outside those defined by the USB 2.0 and USB 3.1Specifications, changing the port sourcing Vbus or V_(CONN), swappingport roles (e.g., between DFP and UFP) and communicating with cables.

The USB Power Delivery Revision 2.0 Specification (hereinafter referredto as the “PD specification”) provides methods and specifications forcommunicating USB PD communication messages between different types ofUSB connectors (e.g., USB Type-A, -B and -C) and legacy applications.For USB Type-A/B connectors, PD communication messages are communicatedon the Vbus line using Binary Frequency Shift Keying (BFSK) encodedsignals. For USB Type-C connectors, PD communication messages arecommunicated on the CC line using Bi-phase Mark Coded (BMC) encodedsignals.

In Bi-phase Mark Coding, a ‘0’ is encoded using one transition at thestart of every bit time (UI), while two transitions per UI (i.e., one atthe start and one in the middle of the UI) is used to encode a ‘1’. Theencoded data signals are driven on the CC line by a data driver ortransmitter with an output voltage swing (vSwing) between 1.05V and1.2V, per the BMC transmitter specifications defined in table shownbelow. When transmitting BMC encoded PD messages, the transmitter mustalso meet other specifications, as defined in the table below.

TABLE Reproduced from Table 5-25 of USB Power Delivery SpecificationRevision 2.0 (v1.1) Name Description Min Nom Max Units tEndDriveBMC Timeto cease driving the 23 μs line after the end of the last bit of theFrame. tFall Fall Time 300 ns tHoldLowBMC Time to cease driving the 1 μsline after the final high-to-low transition. tRise Rise Time 300 nsvSwing Voltage Swing 1.05 1.125 1.2 V zDriver Transmitter output 33 75 Ωimpedance

In the BMC signaling scheme, each PD communication message frame orpacket includes a preamble, a start of packet (SOP) bit(s), a payload, acyclic redundancy check (CRC) bit(s) and an end of packet (EOP) bit(s).As set forth in the PD specification, the transmitter circuit must beginby transmitting a logic low level (i.e., logic ‘0’) when sending thefirst bit of the preamble of each message frame, and must terminate thefinal bit of each message frame with a trailing edge (e.g., alow-to-high transition or a high-to-low transition) to ensure that adownstream receiver properly receives the final bit.

If the trailing edge is a high-to-low transition, the PD specificationdictates that the transmitter circuit should drive the CC line low for aduration of tHoldLowBMC and continue to drive the CC line low for aduration of tEndDriveBMC (as measured from the trailing edge of thefinal bit of the frame), before releasing the CC line to a highimpedance state. If the trailing edge is a low-to-high transition, thePD specification states that the transmitter should continue to drivethe CC line high for one UI, then drive the CC line low for a durationof tHoldLowBMC and continue to drive the CC line low for a duration oftEndDriveBMC (as measured from the trailing edge of the final bit of theframe), before releasing the CC line to the high impedance state. The PDspecification further specifies that each bit of the transmitted signalshould have a rise time no faster than tRise (e.g., 300 ns) and a falltime no faster than tFall (e.g., 300 ns).

In many cases, the transmitter circuit may exhibit a well-controlledslew rate when transitioning from a logic ‘0’ to a logic ‘1’ bit whenthe voltage state on the CC line is known (e.g., when transmitting bitsother than the first bit of the message frame). However, a problemarises during the first bit transmission, such as when transmitting thefirst bit in the preamble of the PD communication message frame.

Before the transmitter circuit can begin driving the CC line, the PDspecification dictates that the CC line should be placed in a highimpedance state, where its voltage is defined by the pull-up resistors,Rp, (or pull-up current source, Ip) and pull-down resistors, Rd, in theDFP and UFP. Depending on the value of Rp/Ip, Rd and the supply voltage(e.g., 3.3 V), the CC line voltage can vary from about 0.25 V to about2.45 V when placed in the high impedance state. When the transmittercircuit is initially connected to the CC line for communicating thefirst bit of a PD communication message frame, the transmitter circuitmust drive the CC line from the unknown voltage at the high impedancestate to the logic ‘0’ state whilst meeting the fall time requirement(e.g., 300 ns, as shown in the Table above) set forth in the PDspecification. In addition, a high frequency voltage ringing may beobserved on the CC line during the first bit transmission due to thelarge inductance of the cable 36 connecting DRP 32 to DRP 40. This highfrequency voltage ringing may cause multiple problems, such as creatinga source of electromagnetic interference (EMI) for the whole USB system,creating a source of power loss, and falsely triggering the receiver toturn on.

As described in more detail below, the embodiments described hereinavoid the voltage ringing commonly observed during the first bittransmission and provide a well-controlled slew rate when transmittingBMC encoded PD communication messages on the CC line of a USB cable.According to one embodiment, an improved circuit and method aredisclosed herein for sensing the CC line voltage at the high impedancestate before the transmitter is connected to the CC line, equalizing theoutput of the transmitter circuit to the CC line voltage, and after aprogrammable time delay, connecting the transmitter circuit to the CCline for driving the first and subsequent bits of the BMC encoded PDcommunication message onto the CC line. Such embodiments enable thetransmitter to drive the CC line from the high impedance state to thelogic ‘0’ state (as well as from logic ‘0’ to ‘1’ and from logic ‘1’ to‘0’) at a well-controlled slew rate, while meeting both the rise andfall times set forth in the PD specification. As such, the disclosedembodiments avoid the undesirable problems mentioned above, such as EMIdue to voltage ringing on the CC line, reduced power efficiency duringstart transmission, and false triggering of the receiver.

FIGS. 3-8 illustrate exemplary block diagrams, circuits, methods andstate diagrams in accordance with the embodiments described herein. Asshown in FIG. 3, DRP 32 and DRP 40 each include a BMC PD transceivercircuit 52 and 54 for encoding and transmitting BMC encoded PDcommunication messages onto the CC line of the USB cable 36. In oneembodiment, transceiver circuits 52 and 54 may be coupled for receivingPD communication messages from an on-chip processing device, such as themicrocontroller units (MCUs) 56 and 58 shown in FIG. 3. Whentransmitting BMC encoded PD communication messages on the CC line fromDRP 32 to DRP 40, transmitter circuitry within transceiver circuit 52may be used to transmit the encoded data via the CC line in USB cable 36to receiver circuitry within transceiver circuit 54. The opposite may betrue when transmitting BMC encoded PD communication messages from DRP 40to DRP 32. As shown in FIG. 3, the transceiver circuits 52 and 54 withineach port may be coupled to both CC pins (CC1 and CC2), so that the BMCencoded PD communication messages can be communicated on the CC line ofUSB cable 36 through a connected pair of the CC pins (e.g., CC2 in theexample of FIG. 3) in DRP 32 and DRP 40.

Although not shown in FIG. 3, transmitter circuitry within a downstreamor upstream transceiver (e.g., transceiver 52 within DRP 32 ortransceiver 54 within DRP 40) may be coupled to transmit data onto theCC line. In general, the transmitter circuitry may include a 4 b 5 bencoder and a BMC encoder for encoding the data before the encoded datais transmitted onto the CC line. Receiver circuitry included within anupstream or downstream transceiver (e.g., transceiver 54 within DRP 40or transceiver 52 within DRP 32) may be coupled to receive the encodeddata transmitted on the CC line. The receiver circuitry may generallyinclude a BMC decoder, a SOP detect, and a 5 b 4 b decoder for decodingthe received data. To verify the accuracy of the transmitted data, thetransmitter and receiver circuitry may also include a cyclic redundancycheck (CRC) circuit. In addition to the components typically includedwithin a transceiver configured to communicate BMC encoded PD messages,additional circuitry is included within the downstream and upstreamports to control the slew rate of the transmitted data and avoid voltageringing on the CC line when transmitting the first data bit. Suchadditional circuitry is illustrated in the example embodiments shown inFIGS. 4A-B and 5A-B.

FIG. 4A illustrates a simplified circuit diagram of additional circuitry60 that may be added to a DRP, which is configured to operate as a UFP(e.g., DRP 32 of FIG. 3). FIG. 4B illustrates a simplified circuitdiagram of additional circuitry 60 that may be added to a DRP, which isconfigured to operate as a DFP (e.g., DRP 40 of FIG. 3). According toone embodiment, the additional circuitry 60 may generally include amultiplexer 64, an amplifier 66, a controller 68 and a plurality ofswitches SW1 . . . SW5.

As shown in FIGS. 4A-B, multiplexer 64 may be coupled for receivingtransmit data (TX data) from a transmit driver 62, which in turn, may becoupled for receiving BMC encoded data (BMC data) from a BMC encoder, asmentioned above. In the embodiments shown in FIG. 4A-B, the transmitdata is supplied to a first input (e.g., input ‘0’) of multiplexer 64,while a second input (e.g., input ‘1’) of the multiplexer is coupledthrough a first switch (i.e., SW1) to the connected CC pin (e.g., CC1 orCC2). As described in more detail below, a select signal (sel) may besupplied to a select input (S) of multiplexer 64 to switch betweentransmitting data and sensing a voltage generated at the CC pin.

As shown in FIGS. 4A-B, the output of multiplexer 64 is coupled to apositive input of amplifier 66, which may be a differential tosingle-ended amplifier, in one embodiment. The negative input ofamplifier 66 is coupled through a second switch (i.e., SW2) to theconnected CC pin (e.g., CC1 or CC2). The output of amplifier 66 iscoupled through a fourth switch (i.e., SW4) to the negative input ofamplifier 66, and through a fifth switch (i.e., SW5) to the connected CCpin.

In the embodiments shown in FIGS. 4A-B, a third switch (i.e., SW3) isincluded within each port to establish current flow from a currentsource (Ip) (or voltage source and pull-up resistor, Rp) in one port toa pull-down resistor (Rd) and ground connection in the other port. Thisthird switch is illustrated in FIG. 3 as switch 42. When a DRP operatesas a UFP (e.g., DRP 32 of FIG. 3), the third switch is actuated toenable current to flow from a current source (Ip) in the downstream port(e.g., DRP 40 of FIG. 3) to the pull-down resistor (Rd) and groundconnection in the upstream port. This is shown in FIG. 4A byillustrating the third switch as coupled between the CC pin and Rd. Whena DRP operates as a DFP (e.g., DRP 40 of FIG. 3), the third switch isactuated to enable current to flow from a current source (Ip) in theupstream port (e.g., DRP 32 of FIG. 3) to the pull-down resistor (Rd)and ground connection in the downstream port. This is shown in FIG. 4Bby illustrating the third switch as coupled between the current sourceand the CC pin. Although not explicitly illustrated in FIGS. 4A-B, eachport includes its own current source (Ip) (or voltage source and pull-upresistor, Rp) and pull-down resistor (Rd), but will connect only one tothe CC pin, depending on the designated port role.

Current flow through the pull-down resistor (Rd) generates a voltage atthe connected CC pins of the downstream and upstream ports. As notedabove, the voltage generated at the connected CC pin may be dependent onthe value of Ip (or Rp), Rd and Vbus, and may vary over a substantiallywide range (e.g., between about 0.25 V and about 2.45 V) when the CCline is placed in the high impedance state.

Before the transmitter circuit is connected to the CC line fortransmitting encoded data, a select signal of ‘1’ may be supplied to theselect input of multiplexer 64 and the first switch may be closed todetect the voltage generated at the CC pin of the transmitting port andset the voltage (TxVo) at the output of amplifier 66 equal to thevoltage detected at the CC pin. In some embodiments, the fourth switch(i.e., SW4), which is coupled in parallel between the output andnegative terminal of amplifier 66, may be closed prior to closing thefirst switch. As described in more detail below, the first switch may beclosed for equalizing the TxVo and CC pin voltages before transmittingthe first data bit. After the TxVo and CC pin voltages are equalized,the output of amplifier 66 may be coupled through the fifth switch(i.e., SW5) to the connected CC pin (e.g., CC1 or CC2) for connectingthe transmitter circuit to the CC line of the USB cable 36 when thefifth switch is closed. The negative input of the amplifier 66 may alsobe coupled to the connected CC pin through the second switch (i.e., SW2)when the fifth switch is closed. After a programmable time delay, thefourth switch may be opened to drive the transmit data onto the CC line.

As shown in FIGS. 4A-B, controller 68 may be coupled for controlling thestate of multiplexer 64 and switches SW1 . . . SW5. In some embodiments,controller 68 may reside within the BMC PD transceiver circuits 52 and54 shown, for example, in the upstream and downstream facing ports ofFIG. 3. However, controller 68 is not necessarily restricted to residingwithin transceiver circuits 52 and 54, and may reside elsewhere in otherembodiments of the disclosure.

According to one embodiment, controller 68 may comprise a digital logicblock. The digital logic block of controller 68 may comprise a sequenceof logic components (such as flip flop(s), inverter(s) and logicgate(s)), which are coupled for supplying a sequence of control signalsto the multiplexer 64 and the switches SW1 . . . SW5 shown in FIGS. 4-5.According to one embodiment, these logic components may implement astate machine, as shown for example in FIG. 8. As described in moredetail below, controller 68 may supply the sequence of control signalsto multiplexer 64 and to switches SW1 . . . SW5 for equalizing the TxVoand CC pin voltages before the amplifier output is connected to the CCpin and the transmit data is driven onto the CC line.

FIGS. 5A and 5B provide slightly more detailed circuit diagrams of theadditional circuitry 60 respectively shown in FIGS. 4A and 4B. Theadditional circuitry 60 shown in FIGS. 5A-5B includes many of the samecircuit components shown in the simplified circuit diagrams of FIGS.4A-B and described above. Similar circuit components are denoted withthe same reference numerals in FIGS. 4 and 5. As in FIGS. 4A-B, forexample, the additional circuitry 60 shown in FIGS. 5A-B includesmultiplexer 64, amplifier 66, controller 68 and switches SW1, SW2, SW3,SW4 and SW5. Description of these components will not be reiteratedbelow for the purpose of brevity.

According to one embodiment, the transmit driver 62 shown in blockdiagram form in FIGS. 4A-B is illustrated in FIGS. 5A-B as comprisingdata buffer 70, operational amplifier 72, a pair of switches 74 andvoltage divider circuit 76. As shown in FIGS. 5A-B, data buffer 70 maybe coupled for receiving BMC encoded data (BMC data) from a BMC encoder.The output of data buffer 70 may be coupled to operational amplifier 72through the pair of switches 74 and voltage divider circuit 76.

When configured to transmit BMC encoded data, switches 74 may beselectively actuated for supplying a transmit (Tx) node voltage to the‘0’ input of multiplexer 64. Operational amplifier 72 may compare andset the Tx_ref node voltage equal to a reference voltage (Vbg) supplied,e.g., by a bandgap reference voltage generator (not shown). Voltagedivider circuit 76 may divide the Tx_ref node voltage by a ratio ofR1/(R1+R1) to generate the transmit (Tx) node voltage, which may besupplied to the ‘0’ input of multiplexer 64. When BMC data is ‘0’, thelower switch 74 may be closed and the upper switch 74 may be opened tosupply a relatively low voltage (e.g., 0V) to the ‘0’ input ofmultiplexer 64. When BMC data is ‘1’, the lower switch 74 may be openedand the upper switch 74 may be closed for supplying a relatively highervoltage (e.g., Vbg/2 V) to the ‘0’ input of multiplexer 64.

In the exemplary embodiments shown in FIGS. 5A-B, operational amplifier72 is coupled between an input supply voltage (Vext) and ground.According to one embodiment, the input supply voltage (Vext) may rangebetween about 2.1 V and about 3.6 V. In one example, operationalamplifier 72 may provide a relatively low closed loop gain (e.g., about1), but may provide a relatively high open loop gain (e.g., about 100dB). The resistance of the R1 resistors included within voltage dividercircuit 76 may be equal, and may be small enough to ensure adequatesettling time at the positive input of the amplifier 66. In one example,the resistance of the R1 resistors may range between about 30 kΩ andabout 50 kΩ, and may be about 40 kΩ in one embodiment.

In some embodiments, switches SW1-SW5 may reside within the pad of thetransmitting port. In other embodiments, switches SW1-SW5 may residewithin the transmitting port, but outside of the pad. In the embodimentsof FIGS. 5A-B, switches SW1, SW2, SW3 and SW5 are illustrated asresiding within the pad (34 or 38) of the transmitting port, along withIp/Rp and Rd. Although not explicitly illustrated in FIGS. 4-5, it isnoted that each port may include two SW1 switches, two SW2 switches, twoSW3 switches and two SW5 switches, i.e., one set of switches SW1, SW2,SW3 and SW5 for each CC pin. By locating these switches within the pad,the transmitter circuit may be connected through the switches to eitherthe CC1 pin or the CC2 pin. Because the fourth switch SW4 resides withinthe transmitter circuit, only one SW4 switch may be needed.

As shown in FIGS. 5A-B, each port may further include a plurality ofswitches 78 and electrostatic discharge resistors (Resd) 80 for each CCpin. For example, a first switch 78 and a first ESD resistor 80 may becoupled in series between each CC pin and switch SW2, while a secondswitch 78 and a second ESD resistor 80 may be coupled in series betweeneach CC pin and switch SW5. Switches 78 and ESD resistors 80 may also beincluded within the pad, and may be used for providing 5V and ESDprotection and improving the reliability of the design.

In some embodiments, stability may be improved by providing amplifier 66with a closed loop gain greater than 1. In one example, the closed loopgain of amplifier 66 may be 2. To ensure an overall gain of 1, a firstvoltage divider circuit 82 may be coupled between switch SW1 and the ‘1’input of multiplexer 64, and a second voltage divider circuit 84 may becoupled between SW2, SW4 and the negative input of amplifier 66 in FIGS.5A-B. Voltage divider circuits 82 and 84 divide the CC pin voltage andthe sensed node voltage by 2, so that when multiplied by the amplifiergain, a TxVo node voltage substantially equal to the CC pin voltage willbe generated at the output of the amplifier.

Generally speaking, the resistance of the R2 resistors included withinthe first voltage divider circuit 82 may be equal, and the resistance ofthe R3 resistors included within second voltage divider circuit 84 mayalso be equal. In one example embodiment, the resistance of the R2resistors may be about 90 kΩ and the resistance of the R3 resistors maybe about 130 kQ Although the value of resistors R2 and R3 may be equalto each other in some embodiments, other embodiments may use differentresistance values for R2 and R3.

FIG. 6 illustrates an exemplary embodiment of a method 90 to transmitBMC encoded data signals across a USB cable from a transmitter circuitincluded within a transmitting port of a USB Type-C connector to areceiver circuit included within a receiving port another USB Type-Cconnector. The method illustrated in FIG. 6 enables the transmittercircuit of the transmitting port to control the slew rate of eachtransition, or edge, of a BMC encoded data signal, including the initialtransition from the high impedance state to the logic ‘0’ state whentransmitting the first bit of the BMC encoded data signal, while meetingthe rise and fall times set forth in the PD specification. In doing so,the illustrated method avoids the undesirable problems mentioned above,such as voltage ringing on the CC line, reduced power efficiency duringstart transmission, and false triggering of the receiver.

Before method 90 begins, switch SW3 may be closed to designate thetransmitting port as either a DFP or an UFP, switch SW4 may be closed totie the output node and negative input of amplifier 66 together, andswitches SW1, SW2, and SW5 may be opened to disconnect the output nodeof the amplifier (and thus, the output node of the transmitter circuit)from the connected CC pin. As noted above with respect to FIGS. 4-5,closing switch SW3 may enable current to flow from a current source (Ip)in one port to a pull-down resistor (Rd) and ground connection inanother port, and this current flow may enable a voltage (V_(CCpin)) tobe generated at the connected CC pins.

According to one embodiment, method 90 may begin by sensing the voltage(V_(CCpin)) generated at the connected CC pin of the transmitting portin step 92, and setting the voltage (TxVo) at the output node ofamplifier 66 equal to the sensed CC pin voltage in step 94. This may beachieved, in one embodiment, by supplying a sel=‘1’ signal tomultiplexer 64 and a close signal to switch SW1. Closing switch SW1provides the CC pin voltage (or a voltage proportional to the CC pinvoltage in the embodiments of FIGS. 5A-B) to the positive terminal ofamplifier 66. Because the output and the negative input of amplifier 66are coupled together through switch SW4, amplifier 66 drives the voltage(TxVo) at the output node of the amplifier to the CC pin voltage(V_(CCpin)), thereby driving the output node of the transmitter circuitto the sensed CC pin voltage. During steps 92 and 94, all other switchesremain in their previous state (e.g., SW3 and SW4 remain closed and SW2and SW5 remain open), and the output node of the transmitter circuitremains disconnected from the CC pin. After a time delay (e.g., about 3μs) sufficient for amplifier 66 to sense and equalize the CC pinvoltage, a sel=‘0’ signal is supplied to multiplexer 64, an open signalis supplied to switch SW1, and a close signal is supplied to switchesSW2 and SW5 to connect the output node of the transmitter circuit to theCC pin in step 96, and transmit the BMC encoded data onto the CC line ofthe USB cable 36 in step 98. Switch SW4 may be opened a short time delay(e.g., about 5 ns) after switches SW2 and SW5 are closed.

As noted above, the CC line of the USB cable 36 is released to the highimpedance state a short time after the final bit of every PDcommunication message is transmitted, and remains in the high impedancestate until the first bit of a subsequent PD communication message istransmitted. In the high impedance state, the CC line voltage is unknownand can vary widely (e.g., between about 0.25V and about 2.45 V). Byequalizing the output node voltage (TxVo) to the sensed CC pin voltage(in step 94), the method show in FIG. 6 enables the transmitter circuitto drive the TxVo output node voltage to a known voltage (e.g.,V_(CCpin)=IpRd) before the output node of the transmitter circuit isconnected to the CC pin (in step 96). This enables the transmittercircuit to more precisely control the initial transition from the CC pinvoltage sensed during the high impedance state to the logic ‘0’ statewhen transmitting the first bit of the PD communication message, and asa result, enables the transmitter circuit to meet the fall timespecification (e.g., 300 ns) for the first bit transmission.

In some embodiments, additional circuit elements may be included withinthe circuitry 60 shown in FIGS. 4-5 to enable the voltage at the CC pinto be accurately sensed and to control the slew rate for eachtransition, or edge, of the BMC encoded data signal, which istransmitted after the first bit transmission. These additional circuitelements are shown in the circuit diagram of FIG. 7 as transistor 86 andcapacitor 88.

As shown in the embodiment of FIG. 7, the TxVo output of amplifier 66may be coupled to the gate of transistor 86, which is coupled betweenthe supply voltage (Vext) and switch SW5. By coupling transistor 86 insuch a manner, the error voltage drop across switch SW5, switch 78 andResd resistor 80 can be canceled by sensing the CC pin voltage (Vcc)through the current path established through Resd resistor 80, switch78, switch SW2, and voltage divider 84 to the negative input ofamplifier 66. In the embodiment shown in FIG. 7, the CC pin voltage(Vcc) generated across the load (Zload) is accurately sensed byproviding the main loop with a high open loop gain, so that the mainloop will ensure that the positive input of amplifier 66 is equal to thenegative input of amplifier 66. In FIG. 7, the main loop extends fromthe TxVo output node to the drain of transistor 86, to switch SW5,switch 78, and Resd resistor 80, to CC, to Resd resistor 80, switch 78,and switch SW2, to R3 and back to the negative input of amplifier 66.

In order to control the slew rate for each transition of the BMC encodeddata signal, a two pole amplifier design is provided to improve thefrequency response and stability of amplifier 66. This is achieved, inthe embodiment of FIG. 7, by coupling capacitor 88 between the TxVooutput of amplifier 66 and the node at switch SW2, which is coupledthrough voltage divider 84 to the negative input node of the amplifier66. By inserting capacitor 88 between the input and output of amplifier66, the non-dominant pole at the CC pin (Vcc) is moved to a higherfrequency, while the dominant pole at the TxVo output of amplifier 66 ismoved to a lower frequency. This pole movement increases the stabilityof amplifier 66 and maintains a consistent slew rate and bandwidth,thereby enabling the transmitter to achieve consistent rise and falltimes. Amplifier stability is maintained in the embodiment of FIG. 7even when switching between the CC1 and CC2 pins.

As described above, the method 90 shown in FIG. 6 may be implemented bysupplying a sequence of control signals to the multiplexer 64 and theswitches (SW1 . . . SW5) included within the additional circuitry 60shown, e.g., in FIGS. 4A-B and 5A-B. As further noted above, thesequence of control signals may be provided by a controller, such ascontroller 68 shown in FIGS. 4A-B and 5A-B and described above.According to one embodiment, the method steps shown in FIG. 6 and/or thesequence of control signals described above may be implemented by, orperformed under the control of a digital logic block included withincontroller 68. According to another embodiment, the method steps shownin FIG. 6 and/or the sequence of control signals described above may beimplemented by, or performed under the control of program instructions,which may be stored within and/or executed by an on-chip controller orprocessing device, such as the microcontroller units (MCUs) 56 and 58shown in FIG. 3. In one example, the digital logic block or the programinstructions executed by an on-chip controller or processing device mayimplement a state machine for controlling the state of the multiplexerand switches shown in FIGS. 4 and 5.

FIG. 8 illustrates an exemplary state diagram for a state machineimplementation. Prior to the initial state (state 0), a close signal maybe supplied to switch SW3 to establish current flow at the CC pin andgenerate a CC pin voltage (V_(CCpin)) across the pull-down resistor (Rd)in either the upstream or downstream facing port. As noted above, switchSW3 may be closed when the port was designated as an upstream facingport or a downstream facing port, and may remain closed until the portrole is changed.

In the initial state (state 0) shown in FIG. 8, a sel=‘0’ signal may besupplied to the select input of multiplexer 64, a close signal may besupplied to switch SW4 to tie the output node of amplifier 66 to thenegative input of amplifier 66, and open signals may be supplied toswitches SW1, SW2 and SW5 to disconnect the output of the amplifier 66(and thus, the output of the transmitter circuit) from the connected CCpin. In state 1, a sel=‘1’ signal may be supplied to the select input ofmultiplexer 64 and a close signal may be supplied to switch SW1 to sensethe CC pin voltage (V_(CCpin)) and set the voltage (TxVo) at the outputnode of amplifier 66 equal to the sensed CC pin voltage. Switches SW3and SW4 remain closed and switches SW2 and SW5 remain open in state 1.After a short time delay (e.g., about 3 μs), a sel=‘0’ signal may besupplied to the select input of multiplexer 64, an open signal may besupplied to switch SW1, and close signals may be supplied to switchesSW2 and SW5 (in state 2) to connect the output node of the transmittercircuit to the CC pin and transmit the encoded data bits onto the CCline of the USB cable 36. A short time delay (e.g., about 5 ns) afterswitches SW2 and SW5 are closed, an open signal may be supplied toswitch SW4 in state 3, and the state of the multiplexer and switches mayremain in state 3 until the final bit of the encoded data istransmitted. After the final bit transmission, the CC line may be heldfor a minimum duration of tHoldLowBMC (e.g., at least 1 μs) before theCC line may be released to the high impedance state and the state of themultiplexer and switches may return to state 0.

It will be appreciated to those skilled in the art having the benefit ofthis disclosure that this disclosure is believed to provide a system,USB Type-C connector and method to transmit Bi-phase Mark Coding (BMC)encoded data signals across a configuration channel (CC) line of a USBcable connecting a transceiver within a transmitting port to atransceiver within a receiving port of the system. In the presentdisclosure, additional circuitry is provided within an upstream anddownstream port to control the slew rate of each transition, or edge, ofa BMC encoded data signal transmitted from the transceiver circuit,while meeting the rise and fall times set forth in the PD specification.The additional circuitry and methods described herein enable thetransceiver circuit to control the slew rate and meet the specified riseand fall times during all transitions of the BMC encoded data signal,including the initial transition from the high impedance state to thelogic ‘0’ state and each subsequent rising and falling edge transition.In doing so, the additional circuitry and methods described herein avoidmany undesirable problems, such as voltage ringing on the CC line,reduced power efficiency during start transmission, and false triggeringof a receiver within an upstream USB Type-C connector.

FIG. 9 is a graph illustrating the voltage ringing that typically occurson the CC line (dashed line) when the pad initially becomes active (“padactive”), such as when transitioning from the high impedance state tothe logic ‘0’ state during the first bit transmission, and the slew ratecontrol (solid line) provided by the additional circuitry 60 and method90 disclosed herein.

As shown in FIG. 9, the voltage at the CC pin can “ring” (dashed line)when the pad is initially activated due to the unknown voltage on the CCline (e.g., about 0.25 V to about 2.45 V) during the high impedancestate and the large cable inductance (e.g., about 640 nH) of an attachedUSB cable. This voltage ringing is undesirable, as it may prevent thetransmitter circuit from meeting the fall time requirement set forth inthe PD specification, and may falsely trigger an upstream receivercircuit to turn on. FIG. 9 further illustrates that when the additionalcircuitry 60 and method 90 disclosed herein are employed (solid line),voltage ringing is avoided and a well-controlled slew rate is achievedwhen transitioning from the high impedance state to the logic ‘0’ stateduring the first bit transmission.

Further modifications and alternative embodiments of various aspects ofthe disclosure will be apparent to those skilled in the art in view ofthis description. It is to be understood that the various embodiments ofthe system, USB Type-C connectors, and methods shown and describedherein are to be taken as the presently preferred embodiments. Elementsand materials may be substituted for those illustrated and describedherein, parts and processes may be reversed, and certain features of thedisclosed embodiments may be utilized independently, all as would beapparent to one skilled in the art after having the benefit of thisdisclosure. It is intended, therefore, that the following claims beinterpreted to embrace all such modifications and changes and,accordingly, the specification and drawings are to be regarded in anillustrative rather than a restrictive sense.

What is claimed is:
 1. A USB Type-C connector, comprising: a pluralityof switches, each coupled to a configuration channel (CC) pin of the USBType-C connector; a transmitter circuit having an output node switchablycoupled to the CC pin through at least a subset of the plurality ofswitches; and a controller configured to supply a sequence of controlsignals to the transmitter circuit and the plurality of switches to seta voltage at the output node of the transmitter circuit equal to avoltage generated at the CC pin before the output node of thetransmitter circuit is connected to the CC pin to transmit encoded datato the CC pin.
 2. The USB Type-C connector as recited in claim 1,wherein the transmitter circuit comprises a multiplexer comprising afirst input coupled to receive the encoded data, a second input coupledvia a first switch of the plurality of switches to the CC pin, a selectinput, and an output.
 3. The USB Type-C connector as recited in claim 2,wherein the transmitter circuit further comprises an amplifiercomprising: a first input coupled to receive the output from themultiplexer; a second input coupled via a second switch of the pluralityof switches to the CC pin; and an output, which is the output node ofthe transmitter circuit; wherein the amplifier output is coupled via afourth switch of the plurality of switches to the second input of theamplifier and further coupled via a fifth switch of the plurality ofswitches to the CC pin.
 4. The USB Type-C connector as recited in claim3, further comprising a pull-down resistor coupled between the CC pinand a third switch of the plurality of switches, which is coupled toground.
 5. The USB Type-C connector as recited in claim 3, wherein athird switch of the plurality of switches is coupled between a currentsource and the CC pin.
 6. The USB Type-C connector as recited in claim 4or 5, wherein the controller is configured to supply the sequence ofcontrol signals to the select input of the multiplexer and to the first,second, third, fourth and fifth switches to equalize the voltage at theamplifier output to the voltage at the CC pin before the amplifieroutput is connected to the CC pin to transmit the encoded data to the CCpin.
 7. The USB Type-C connector as recited in claim 6, wherein thecontroller is configured to supply a close signal to the third switch toestablish current flow through the pull-down resistor and generate thevoltage at the CC pin.
 8. The USB Type-C connector as recited in claim6, wherein the controller is configured to supply: open signals to thefirst, second and fifth switches to disconnect the amplifier output fromthe CC pin; and a close signal to the fourth switch to couple theamplifier output to the second input of the amplifier.
 9. The USB Type-Cconnector as recited in claim 6, wherein the controller is configured tosupply: a select signal to the multiplexer to select the second input ofthe multiplexer; and a close signal to the first switch to sense thevoltage generated at the CC pin and set the voltage at the amplifieroutput equal to the voltage at the CC pin.
 10. The USB Type-C connectoras recited in claim 6, wherein the controller is configured to supply: aselect signal to the multiplexer to select the first input of themultiplexer; and an open signal to the first switch, and close signalsto the second and fifth switches to connect the amplifier output to theCC pin and transmit the encoded data to the CC pin.
 11. The USB Type-Cconnector as recited in claim 10, wherein after the fifth switch isclosed, the controller is configured to supply an open signal to thefourth switch.
 12. A method to transmit encoded data across a USB cablefrom a transmitter circuit included within a transmitting port of a USBType-C connector, the method comprising: detecting a voltage generatedat a configuration channel (CC) pin of the transmitting port; setting avoltage at an output node of the transmitter circuit equal to thevoltage detected at the CC pin before the output node is connected tothe CC pin; subsequently connecting the output node of the transmittercircuit to the CC pin through at least one switch; and transmitting theencoded data from the transmitter circuit through the CC pin to the USBcable.
 13. The method as recited in claim 12, wherein: the USB Type-Cconnector comprises a first switch, a second switch, a third switch, afourth switch and a fifth switch, wherein the third switch is coupledto: (a) a pull-down resistor, (b) a current source, or (c) a voltagesource and a pull-up resistor; and the transmitter circuit comprises: amultiplexer comprising a first input coupled to receive the encodeddata, a second input coupled via the first switch to the CC pin, aselect input, and an output; and an amplifier comprising a first inputcoupled to receiving the output from the multiplexer, a second inputcoupled via the second switch to the CC pin, and an output, which is theoutput node of the transmitter circuit, wherein the amplifier output iscoupled via the fourth switch to the second input of the amplifier andfurther coupled via the fifth switch to the CC pin.
 14. The method asrecited in claim 13, wherein prior to the step of detecting a voltage,the method comprises: supplying a close signal to the third switch togenerate the voltage at the CC pin; supplying a close signal to thefourth switch to couple the amplifier output to the second input of theamplifier; and supplying open signals to the first, second and fifthswitches to disconnect the amplifier output from the CC pin.
 15. Themethod as recited in claim 13, wherein the step of detecting a voltagegenerated at the CC pin and the step of setting a voltage at an outputnode of the transmitter circuit comprise: supplying a select signal tothe multiplexer to select the second input of the multiplexer circuit;and supplying a close signal to the first switch to detect the voltagegenerated at the CC pin and set the voltage at the amplifier outputequal to the voltage detected at the CC pin.
 16. The method as recitedin claim 13, wherein the step of subsequently connecting the output nodeof the transmitter circuit and the step of transmitting the encoded datacomprise: supplying a select signal to the multiplexer to select thefirst input of the multiplexer; supplying an open signal to the firstswitch, and close signals to the second and fifth switches to connectthe amplifier output to the CC pin and transmit the encoded data fromthe transmitter circuit through the CC pin to the USB cable.
 17. Themethod as recited in claim 16, wherein after the fifth switch is closed,the method further comprises supplying an open signal to the fourthswitch.
 18. A system comprising a first USB Type-C connector coupled toa second USB Type-C connector via a USB cable, wherein the first USBType-C connector comprises: at least one configuration channel (CC) pin;a plurality of switches, each coupled to the at least one CC pin; atransmitter circuit having an output node, which is switchably coupledto the at least one CC pin through at least a subset of the plurality ofswitches to transmit encoded data across the USB cable to a CC pin ofthe second USB Type-C connector; and a controller configured to supply asequence of control signals to the transmitter circuit and the pluralityof switches to set a voltage at the output node of the transmittercircuit equal to a voltage generated at the at least one CC pin beforethe output node of the transmitter circuit is connected to the at leastone CC pin to transmit the encoded data across the USB cable.
 19. Thesystem as recited in claim 18, wherein the transmitter circuit comprisesa multiplexer comprising a first input coupled to receive the encodeddata, a second input coupled via a first switch of the plurality ofswitches to the CC pin, a select input, and an output.
 20. The system asrecited in claim 19, wherein the transmitter circuit further comprisesan amplifier comprising: a first input coupled to receive the outputfrom the multiplexer; a second input coupled via a second switch of theplurality of switches to the CC pin; and an output, which is the outputnode of the transmitter circuit; wherein the amplifier output is coupledvia a fourth switch of the plurality of switches to the second input ofthe amplifier and further coupled via a fifth switch of the plurality ofswitches to the CC pin.
 21. The system as recited in claim 20, wherein:the first USB Type-C connector further comprises a pull-down resistorcoupled between the at least one CC pin and a third switch of theplurality of switches, which is coupled to ground; the second USB Type-Cconnector comprises: (a) a pull-up resistor coupled between the CC pinand a voltage source, or (b) a current source coupled to the CC pin; andthe controller is configured to: supply open signals to the first,second and fifth switches to disconnect the amplifier output from the atleast one CC pin; and supply a close signal to the third switch toestablish current flow from the pull-up resistor or the current sourcein the second USB Type-C connector through the pull-down resistor in thefirst USB Type-C connector to generate the voltage at the at least oneCC pin.
 22. The system as recited in claim 21, wherein the controller isfurther configured to supply: a close signal to the fourth switch tocouple the amplifier output to the second input of the amplifier; aselect signal to the multiplexer for selecting the second input of themultiplexer; and a close signal to the first switch to detect thevoltage generated at the at least one CC pin and set a voltage at theamplifier output equal to the voltage detected at the at least one CCpin.
 23. The system as recited in claim 22, wherein the controller isfurther configured to supply: a select signal to the multiplexer forselecting the first input of the multiplexer; an open signal to thefirst switch, and close signals to the second and fifth switches toconnect the amplifier output to the at least one CC pin and transmit theencoded data across the USB cable; and an open signal to the fourthswitch after the fifth switch is closed.
 24. The system as recited inclaim 20, wherein: the first USB Type-C connector further comprises athird switch of the plurality of switches, which is coupled between acurrent source and the at least one CC pin or a voltage source andpull-up resistor and the at least one CC pin; the second USB Type-Cconnector comprises a pull-down resistor coupled to ground; and thecontroller is configured to: supply open signals to the first, secondand fifth switches to disconnect the amplifier output from the at leastone CC pin; and supply a close signal to the third switch to establishcurrent flow from the pull-up resistor or the current source in thefirst USB Type-C connector through the pull-down resistor in the secondUSB Type-C connector to generate the voltage at the at least one CC pin.25. The system as recited in claim 24, wherein the controller is furtherconfigured to supply: a close signal to the fourth switch to couple theamplifier output to the second input of the amplifier; a select signalto the multiplexer for selecting the second input of the multiplexer;and a close signal to the first switch to detect the voltage generatedat the at least one CC pin and set a voltage at the amplifier outputequal to the voltage detected at the at least one CC pin.
 26. The systemas recited in claim 25, wherein the controller is further configured tosupply: a select signal to the multiplexer for selecting the first inputof the multiplexer; an open signal to the first switch, and closesignals to the second and fifth switches to connect the amplifier outputto the at least one CC pin and transmit the encoded data across the USBcable; and an open signal to the fourth switch after the fifth switch isclosed.